If you’ve ever gone to the grocery store and forgotten that one essential item, the question you face is how quickly can you run back in the store, get that necessary item, and be on your way home? Jeff Wilson of Mentor Graphics says that design teams often feel this way as they approach tapeout, only to be confronted with engineering change orders (ECOs). One major factor—the challenge of re-filling designs.
Phil Garrou provides his analysis of the presentations given at this year’s ISS meeting, focusing on those from IBM, Linx, imec, IHS and IBS. IBM’s Jon Casey, for example, notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.
Pete Singer hasn’t toasted to cheap silicon for a while. Why? Because that mission has been accomplished. At SEMI’s ISS, Paul Farrar, manager of the G450C consortium put the industry progress over the last 40+ years in perspective. “1 Megabyte of memory in 1970 was $750,000. It was sold as an IBM add-on,” he said. “The great technology was made of 57mm wafers, five masking levels, and one level of metal. Today, it’s is less than a penny. That is a 100 million X improvement.”
